The present invention relates generally to the field of advanced thin film deposition methods commonly used in the semiconductor, data storage, flat panel display, as well as allied or other industries. More particularly, the present invention relates to an enhanced sequential or non-sequential atomic layer deposition (ALD) apparatus and technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive thin films.
As integrated circuit (IC) dimensions shrink and the aspect ratios of the resulting features increase, the ability to deposit conformal, ultra-thin films on the sides and bottoms of high aspect ratio trenches and vias becomes increasingly important. These conformal, ultra-thin films are typically used as xe2x80x9clinerxe2x80x9d material to enhance adhesion, prevent inter-diffusion and/or chemical reaction between the underlying dielectric and the overlying metal, and promote the deposition of a subsequent film.
In addition, decreasing device dimensions and increasing device densities has necessitated the transition from traditional CVD tungsten plug and aluminum interconnect technology to copper interconnect technology. This transition is driven by both the increasing impact of the RC interconnect delay on device speed and by the electromigration (i.e., the mass transport of metal due to momentum transfer between conducting electrons and diffusing metal atoms, thereby affecting reliability) limitations of aluminum based conductors for sub 0.25 xcexcm device generations. Copper is preferred due to its lower resistivity and higher (greater than 10 times) electromigration resistance as compared to aluminum. A single or dual damascene copper metallization scheme is used since it eliminates the need for copper etching and reduces the number of integration steps required. However, the burden now shifts to the metal deposition step(s) as the copper must fill predefined high aspect ratio trenches and/or vias in the dielectric. Electroplating has emerged as the copper fill technique of choice due to its low deposition temperature, high deposition rate, and potential low manufacturing cost.
Two major challenges exist for copper wiring technology: the barrier and seed layers. Copper can diffuse readily into silicon and most dielectrics. This diffusion may lead to electrical leakage between metal wires and poor device performance. An encapsulating barrier layer is needed to isolate the copper from the surrounding material (e.g., dielectric or Si), thus preventing copper diffusion into and/or reaction with the underlying material (e.g. dielectric or Si). In addition, the barrier layer also serves as the adhesion or glue layer between the patterned dielectric trench or via and the copper used to fill it. The dielectric material can be a low dielectric constant, i.e. low-k material (used to reduce interand intra-line capacitance and cross-talk) which typically suffers from poorer adhesion characteristics and lower thermal stability than traditional oxide insulators. Consequently, this places more stringent requirements on the barrier material and deposition method. An inferior adhesion layer will, for example, lead to delamination at either the barrier-to-dielectric or barrier-to-copper interfaces during any subsequent anneal and/or chemical mechanical planarization (CMP) processing steps leading to degradation in device performance and reliability. Ideally, the barrier layer should be thin, conformal, defect free, and of low resistivity so as to not compromise the conductance of the copper metal interconnect structure.
In addition, electroplating fill requires a copper seed layer, which serves to both carry the plating current and act as the nucleation layer. The preferred seed layer should be smooth, continuous, of high purity, and have good step coverage with low overhang. A discontinuity in the seed layer will lead to sidewall voiding, while gross overhang will lead to pinch-off and the formation of top voids.
Both the barrier and seed layers which are critical to successful implementation of copper interconnects require a means of depositing high purity, conformal, ultra-thin films at low substrate temperatures.
Physical vapor deposition (PVD) or sputtering has been adopted as the preferred method of choice for depositing conductor films used in IC manufacturing. This choice has been primarily driven by the low cost, simple sputtering approach whereby relatively pure elemental or compound materials can be deposited at relatively low substrate temperatures. For example, refractory based metals and metal compounds such as tantalum (Ta), tantalum nitride (TaNx), other tantalum containing compounds, tungsten (W), tungsten nitride (WNx), and other tungsten containing compounds which are used as barrier/adhesion layers can be sputter deposited with the substrate at or near room temperature. However, as device geometries have decreased, the step coverage limitations of PVD have increasingly become an issue since it is inherently a line-of-sight process. This limits the total number of atoms or molecules which can be delivered into the patterned trench or via. As a result, PVD is unable to deposit thin continuous films of adequate thickness to coat the sides and bottoms of high aspect ratio trenches and vias. Moreover, medium/high-density plasma and ionized PVD sources developed to address the more aggressive device structures are still not adequate and are now of such complexity that cost and reliability have become serious concerns.
Chemical vapor deposition (CVD) processes offer improved step coverage since CVD processes can be tailored to provide conformal films. Conformality ensures the deposited films match the shape of the underlying substrate, and the film thickness inside the feature is uniform and equivalent to the thickness outside the feature. Unfortunately, CVD requires comparatively high deposition temperatures, suffers from high impurity concentrations, which impact film integrity, and have higher cost-of-ownership due to long nucleation times and poor precursor gas utilization efficiency. Following the tantalum containing barrier example, CVD Ta and TaN films require substrate temperatures ranging from 500xc2x0 C. to over 800xc2x0 C. and suffer from impurity concentrations (typically of carbon and oxygen) ranging from several to tens of atomic % concentration. This generally leads to high film resistivities (up to several orders of magnitude higher than PVD), and other degradation in film performance. These deposition temperatures and impurity concentrations make CVD Ta and TaN unusable for IC manufacturing, in particular for copper metallization and low-k integration.
Chen et al. (xe2x80x9cLow temperature plasma-assisted chemical vapor deposition of tantalum nitride from tantalum pentabromide for copper metallizationxe2x80x9d, J. Vac. Sci. Technol. B 17(1), pp. 182-185 (1999); and xe2x80x9cLow temperature plasma-promoted chemical vapor deposition of tantalum from tantalum pentabromide for copper metallizationxe2x80x9d, J. Vac. Sci. Technol. B 16(5), pp. 2887-2890 (1998)) have demonstrated a plasma-assisted (PACVD) or plasma-enhanced (PECVD) CVD approach using tantalum pentabromide (TaBr5) as the precursor gas to reduce the deposition temperature. Ta and TaNx films were deposited from 350xc2x0 C. to 450xc2x0 C. and contained 2.5 to 3 atomic % concentration of bromine. Although the deposition temperature has been reduced by increased fragmentation (and hence, increased reactivity) of the precursor gases in the gas-phase via a plasma, the same fragmentation leads to the deposition of unwanted impurities. Gas-phase fragmentation of the precursor into both desired and undesired species inherently limits the efficacy of this approach.
Recently, atomic layer chemical vapor deposition (AL-CVD) or atomic layer deposition (ALD) has been proposed as an alternative method to CVD for depositing conformal, ultra-thin films at comparatively lower temperatures. ALD is similar to CVD except that the substrate is sequentially exposed to one reactant at a time. Conceptually, it is a simple process: a first reactant is introduced onto a heated substrate whereby it forms a monolayer on the surface of the substrate. Excess reactant is pumped out. Next a second reactant is introduced and reacts with the first reactant to form a monolayer of the desired film via a self-limiting surface reaction. The process is self-limiting since the deposition reaction halts once the initially adsorbed (physi- or chemi-sorbed) monolayer of the first reactant has fully reacted with the second reactant. Finally, the excess second reactant is evacuated. The above sequence of events comprises one deposition cycle. The desired film thickness is obtained by repeating the deposition cycle the required number of times.
In practice, ALD is complicated by the painstaking selection of a process temperature setpoint wherein both: 1) at least one of the reactants sufficiently adsorbs to a monolayer and 2) the surface deposition reaction can occur with adequate growth rate and film purity. If the substrate temperature needed for the deposition reaction is too high, desorption or decomposition of the first adsorbed reactant occurs, thereby eliminating the layer-by-layer process. If the temperature is too low, the deposition reaction may be incomplete (i.e., very slow), not occur at all, or lead to poor film quality (e.g., high resistivity and/or high impurity content). Since the ALD process is entirely thermal, selection of available precursors (i.e., reactants) that fit the temperature window becomes difficult and sometimes unattainable. Due to the above-mentioned temperature related problems, ALD has been typically limited to the deposition of semiconductors and insulators as opposed to metals. ALD of metals has been confined to the use of metal halide precursors. However, halides (e.g., Cl, F, Br) are corrosive and can create reliability issues in metal interconnects.
Continuing with the TaN example, ALD of TaN films is confined to a narrow temperature window of 400xc2x0 C. to 500xc2x0 C., generally occurs with a maximum deposition rate of 0.2 xc3x85/cycle, and can contain up to several atomic percent of impurities including chlorine and oxygen. Chlorine is a corrosive, can attack copper, and lead to reliability concerns. The above process is unsuitable for copper metallization and low-k integration due to the high deposition temperature, slow deposition rate, and chlorine impurity incorporation.
In conventional ALD of metal films, gaseous hydrogen (H2) or elemental zinc (Zn) is often cited as the second reactant. These reactants are chosen since they act as a reducing agent to bring the metal atom contained in the first reactant to the desired oxidation state in order to deposit the end film. Gaseous, diatomic hydrogen (H2) is an inefficient reducing agent due to its chemical stability, and elemental zinc has low volatility (e.g., it is very difficult to deliver sufficient amounts of Zn vapor to the substrate) and is generally incompatible with IC manufacturing. Unfortunately, due to the temperature conflicts that plague the ALD method and lack of kinetically favorable second reactant, serious compromises in process performance result.
In order to address the limitations of traditional thermal or pyrolytic ALD, radical enhanced atomic layer deposition (REALD, U.S. Pat. No. 5,916,365) or plasma-enhanced atomic layer deposition has been proposed whereby a downstream radio-frequency (RF) glow discharge is used to dissociate the second reactant to form more reactive radical species which drives the reaction at lower substrate temperatures. Using such a technique, Ta ALD films have been deposited at 0.16 to 0.5 xc3x85/cycle at 25xc2x0 C., and up to approximately 1.67 xc3x85/cycle at 250xc2x0 C. to 450xc2x0 C. Although REALD results in a lower operating substrate temperature than all the aforementioned techniques, the process still suffers from several significant drawbacks. Higher temperatures must still be used to generate appreciable deposition rates. Such temperatures are still too high for some films of significant interest in IC manufacturing such as polymer-based low-k dielectrics that are stable up to temperatures of only 200xc2x0 C. or less. REALD remains a thermal or pyrolytic process similar to ALD and even CVD since the substrate temperature provides the required activation energy for the process and is therefore the primary control means for driving the deposition reaction.
In addition, Ta films deposited using REALD still contain chlorine as well as oxygen impurities, and are of low density. A low density or porous film leads to a poor barrier against copper diffusion since copper atoms and ions have more pathways to traverse the barrier material. Moreover, a porous or under-dense film has lower chemical stability and can react undesirably with overlying or underlying films, or with exposure to gases commonly used in IC manufacturing processes.
Another limitation of REALD is that the radical generation and delivery is inefficient and undesirable. RF plasma generation of radicals used as the second reactant such as atomic H is not as efficient as microwave plasma due to the enhanced efficiency of microwave energy transfer to electrons used to sustain and dissociate reactants introduced in the plasma. Furthermore, having a downstream configuration whereby the radical generating plasma is contained in a separate vessel located remotely from the main chamber where the substrate is situated and using a small aperture to introduce the radicals from the remote plasma vessel to the main chamber body significantly decreases the efficiency of transport of the second radical reactant. Both gas-phase and wall recombination will reduce the flux of desired radicals that can reach the substrate. In the case of atomic H, these recombination pathways will lead to the formation of diatomic H2, a far less effective reducing agent. If the plasma used to generate the radicals was placed directly over the substrate, then the deposition of unwanted impurities and particles can occur similarly to the case of plasma-assisted CVD.
Finally, ALD (or any derivative such as REALD) is fundamentally slow since it relies on a sequential process whereby each deposition cycle is comprised of at least two separate reactant flow and evacuation steps, which can occur on the order of minutes with conventional valve and chamber technology. Significant improvements resulting in faster ALD are needed to make it more suitable for commercial IC manufacturing.